作者：北京广利核系统工程有限公司 董玲玲，许先音，李梦林

摘要：基于FPGA开发的核电数字化仪控系统（DCS）应用环境苛刻，功能性的故障可能引起误操作，进而引发灾难性的后果，因此对FPGA开发的软件功能的测试尤为重要。传统的界面仿真测试验证效率低、可重用性差，而采用验证方法学的验证平台的搭建又较为繁琐，用时较多，不能满足项目时间的要求。本文提出一种基于System Verilog 搭建的可重用的验证平台，采用虚拟端口方法模拟外部芯片接口的功能，最后采用批处理的方式开启验证平台，实现自动化的仿真测试，其接口模型、算法库及验证平台自启动的框架可在不同的项目测试
中使用，实现可重用性。该平台已在公司的核电站仪控系统产品的验证中得到成功应用，缩短了测试时间，并满足安全级产品认证的要求。

关键词：验证平台；System Verilog；重用性；仿真验证

Abstract: The application environment of the nuclear power digital instrument control system (DCS) developed by FPGA is harsh. Functional failure may cause misoperation,which may lead to disastrous consequences. Therefore it is particularly important to perform functional tests of the software developed by FPGA. The traditional interface simulation test verification efficiency is low and the reusability is poor, while the methodology-based verification platform is a bit complicated and takes a lot of time, which cannot meet the requirements of project time. In this paper, a reusable verification platform based on System Verilog is proposed. By using the method of virtual port to simulate the function of external chip, the verification platform is opened by batch processing to realize automatic simulation test. The verification platform can be used in different project tests to realize reusability. The platform has been successfully applied in the verification of the company's nuclear power plant control system products, which shortens the test time and meets the requirements of safety level product certification.

Key words: Testbench; System Verilog; Reusable; Simulation verification

在线预览：一种可重用的验证平台在核电FPGA仿真测试中的应用

摘自《自动化博览》2019年12月刊